The present invention relates to a semiconductor memory device, and more particularly to a data output buffer of a semiconductor memory device.
In general, noises are important to the operational speed and reliability of semiconductor memory devices. Therefore, considerable research has been conducted to remove noises occurring in chips. The noises that are generated at the data output buffer during the operation of data are especially serious. A technique for reducing noises has been suggested in United Kingdom patent publication No. GB 2 257 856 A.
FIG. 1 shows a conventional data output buffer. In FIG. 1, a pair of data D, D denotes the output signals of a sense amplifier (not shown in FIG. 1) and an output enabling signal OE denotes the signal for enabling the output of the pair of data D, D. As shown in FIG. 1, the data output buffer comprises a data input buffer for receiving the data D and the output enabling signal OE, an inversion data input buffer for receiving the inversion data D and the output enabling signal OE, a data output driver connected to the output terminals of the data input buffer and the inversion data input buffer, a first control circuit 12 for delaying the transition of output signal from the data input buffer during the transition from the "HIGH" state to "LOW" state and a second control circuit 13 for delaying the transition of the output signal from the inversion data input buffer during the transition from the "LOW" state to "HIGH" state.
The data input buffer comprises a NAND gate for receiving the data D and the output enabling signal OE, an inverter 2 for inverting the output signal of the NAND gate 1, a P-MOS transistor 3 having a source electrode in which a voltage source Vcc is supplied, and a gate electrode in which the output signal of the inverter 2 is received, an N-MOS transistor 4 having a source electrode in which a ground potential Vss is supplied, a gate electrode in which the output signal of the inverter 2 is received and a drain electrode connected to a drain electrode of the P-MOS transistor 3.
The inversion data input buffer comprises a NAND gate 6 for receiving the inversion data D and the output enabling signal OE, a P-MOS transistor 7 having a gate electrode in which the output signal of the NAN D gate 6 is received and a source electrode in which the voltage source Vcc is supplied, an N-MOS transistor 8 having a gate electrode in which the output signal of the NAND gate 6 is received, a source electrode to which the ground potential Vss is supplied and a drain electrode connected to a drain electrode of the P-MOS transistor 7.
The data output driver comprises a P-MOS transistor 10 having a gate electrode which receives the output signal of an inverter 5, which is comprised of the P-MOS transistor 3 and the N-MOS transistor 4, and a source electrode in which the voltage source Vcc is supplied and an N-MOS transistor 11 having a gate electrode which receives the output signal of an inverter 9, which is comprised of the P-MOS transistor 7 and the N-MOS transistor 8, a source electrode connected to the ground potential Vss and a drain electrode connected to the drain electrode of the P-MOS transistor 10. Therefore, a data output signal Dout is generated via the common connection point between the N-MOS transistor 11 and the P-MOS transistor 10.
FIG. 1 illustrates an embodiment of a data output buffer according to this invention. In FIG. 1, a first control circuit 12 is shown to comprise a first delay portion 12A and a first slope control portion means 12B. The first delay portion 12A includes a first inverter 14 receiving an output signal Dd from inverter 2, and second and third inverters 15 and 16 both connected in series with the first inverter 14. The first slope control portion means 12B includes a first N-MOS transistor 17 having a gate electrode applied with an output signal S3 from the third inverter 16, a source electrode connected to a ground potential Vss, and a drain electrode connected to the source electrode of an N-MOS transistor 4, and a second N-MOS transistor 18 having a gate electrode applied with a voltage source Vcc and drain and source electrodes connected, respectively, to the drain and source electrodes of the first N-MOS transistor 17. The second N-MOS transistor 18 operates as a constant current source.
A second control circuit 13 includes a second delay portion 13A and a second slope control portion means 13B. Second delay portion 13A comprises a fourth inverter 19 receiving an output signal Dd from NAND gate 6, arid fifth and sixth inverters 20 and 21 both connected in series with the fourth inverter 19. The second slope control portion means 13B comprises a first P-MOS transistor 22 having a gate electrode applied with an output signal $6 from the sixth inverter 21, a source electrode applied with a voltage source Vcc, and a drain electrode connected to the source electrode of a P-MOS transistor 7, and a second P-MOS transistor 23 having a gate electrode applied with a ground potential Vss and drain and source electrodes connected, respectively, with the drain and source electrodes of the first P-MOS transistor 22. The second P-MOS transistor 23 operates as a constant current source.
According to the above, however, because it is carried out to limit the occurrence of noises having no relation with the occurrence of noises and the ramp speed is controlled slowly in low speed under a condition in which the data output driver is turned on, there is a disadvantage in that the operational speed may be reduced.